Solution concentration and several dip cycles are key factors that determine the thickness and quality of perovskite quantum dot (PQD) films. Dip coating is an effective technique used for depositing solution-processed PQDs in substrates which are common passivation layers in solar cells. The optimum dip-coating parameters for depositing cesium lead halide PQDs on GaAs substrates...
Tag: 7
SDG forum and exhibit on WED 2023
Centered on the theme “Leadership in Collaborative Innovations for a Stronger Nation” Supreme Student Council (SSC) Alangilan, the Office of Student Organizations, the Center for Innovations in Engineering Education (CIEE), and the College of Engineering organized the Sustainable Development Forum on the second day of celebrating the World Engineering Day 2023. The forum shed light...
DevCom, CSD collab for SDG exhibit
BS Development Communication students in collaboration with the Center for Sustainable Development staged a one-day exhibit that highlighted the University’s sustainable initiatives in the achievement of the 17 UN SDGs. DevCom students featured various sustainability efforts through a wide array of IEC materials such as pamphlets, brochures, dioramas, charts, and diagrams as well as videos...
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder
Low-power and high-speed calculation is very important nowadays for energy-efficient demand of electronic devices. With the usage of ANT (All-N-transistor) logic, the speed constraint caused by PMOS transistors can be overcome through an auxiliary current path across NMOS transistors. This study presents a 800-MHz 28.8-mW 8-bit carry look-ahead adder (CLA) using ANT logic implemented on...
Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load
This research illustrates a DC–DC buck converter with a pulse width modulation (PWM) feedback control loop and capable of power supply voltage range from VDD to 2.5× VDD, which is equivalent to 5–14 V. It is a single chip with area of 1.379 × 0.813 mm2 using 0.5 µm HV CMOS process, where high voltage (HV) MOSFETs, a Dead-time detector, a...
